FIG. 14 is a block diagram showing configuration of a voltage controlling/oscillating device based on the conventional technology. This voltage controlling/oscillating device 1 comprises a delay unit 11, a delay interpolator 12, and an inverting gate 13. A signal outputted from the output terminal OUT1 of the delay interpolator 12 is finally outputted from an output terminal 15 of the voltage controlling/oscillating device 1 to an external device as a clock signal CLK. The same signal as the output signal is also inputted into the inverting gate 13. The signal inputted into the inverting gate 13 is inputted with the phase thereof inverted into a first input terminal FST1 of the delay interpolator 12 and delay unit 11. The signal inputted into the delay unit 11 is delayed by a preset delay rate d1 and inputted into a second input terminal SLW1 of the delay interpolator 12. An oscillation frequency control voltage (Namely, a voltage for controlling the oscillation frequency) VCTL is inputted into a control terminal CTL1 of the delay interpolator 12 through an oscillation frequency control terminal 14 of the voltage controlling/oscillating device 1.
FIG. 15 is a circuit diagram showing detailed configuration of the voltage controlling/oscillating device 1. The delay unit 11 comprises four pieces of first to fourth transistors 101, 102, 103, and 104; three pieces of first to third current sources 105, 106, and 107; two pieces of resistors 108 and 109; and two pieces of capacitors 110 and 111, and constitute a differential switching circuit and an emitter follower. The circuit constant of the delay unit 11 is designed in such a way that a propagation delay between input and output thereof will be a desired delay rate d1.
The first transistor 101 of the differential switching circuit is connected to an input terminal IN of the delay unit 11 at the base terminal thereof, the collector terminal thereof is connected to a power supply terminal VCC through the loading resistor 108, and the emitter terminal thereof is connected to the first current source 105. The second transistor 102 of the differential switching circuit is connected to an inverting input terminal /IN (expressed with a bar over IN in the figure) of the delay unit 11 at the base terminal thereof, the collector terminal thereof is connected to the power supply terminal VCC through the loading resistor 109, and the emitter terminal thereof is connected to the first current source 105. The collector terminal of the first transistor 101 is connected to one electrode of the capacitor 110 and the collector terminal of the second transistor 102 is connected to one electrode of the capacitor 111, and the other electrodes of these capacitors are connected to the power supply terminal VCC. It should be noted that the symbol "/" in front of a terminal symbol in this specification represents that an inverted signal of an input or an output signal to a terminal with the same terminal symbol is inputted or outputted.
The collector terminal of the second transistor 102 is connected to the base terminal of the third transistor 103 of the emitter follower. In the third transistor 103, the collector terminal is connected to the power supply terminal VCC, and the emitter terminal is connected to the second current source 106 as well as to the output terminal OUT of the delay unit 11. The collector terminal of the first transistor 101 is connected to the base terminal of the fourth transistor 104 as the emitter follower. In the fourth transistor 104, the collector terminal is connected to the power supply terminal VCC, and the emitter terminal is connected to the third power supply terminal 107 as well as to the inverting output terminal /OUT of the delay unit 11. The output terminal /OUT and inverting output terminal /OUT of the delay unit 11 are connected to the second input terminal SLW1 and second inverting input terminal /SLW1 of the delay interpolator 12 respectively.
Herein, it is assumed that waveforms of signals inputted into the first input terminal FST1 and the second input terminal SLW1 of the delay interpolator 12 are Vfst (t) and Vslw (t); each input resistance, input capacity and delay constant of the first and second transistors 101 and 102 are rb, Cdif, and Kdif respectively. Further, it is assumed that each input capacity and delay constant of the third and fourth transistors 103 and 104 are Ceh and Keh respectively; and a cutoff angle frequency of the transistor is .omega.t. Also, it is assumed that the resistance of the resistors 108 and 109 is RL. Further, it is assumed that the current of the first current source 105 is IEE0, and the current of the second and third current sources 106 and 107 is IEE1. Then, the propagation delay d1 in the delay unit 11 can be expressed with the help of the following Equation (1). EQU d1=Vslw(t)-Vfst(t)=rb/ (RL.multidot..omega.t)+rb.multidot.Cdif+In(2).multidot.RL.multidot.Ceh=rb/ (RL.multidot..omega.t)+rb.multidot.Kdif.multidot.IEE0+In(2).multidot.RL.mul tidot.Keh.multidot.IEE1 (1)
The first term and second term in the right side of this Equation (1) corresponds to a switching delay rate in the pair of differential transistors respectively, and the third term therein corresponds to a propagation delay rate in the emitter follower.
The delay interpolator 12 comprises eight pieces of the fifth to twelfth transistors 201, 202, 203, 204, 205, 206, 207, and 208; three pieces of the fourth to sixth current sources 209, 210, and 211; four pieces of resistors 212, 213, 214, and 215; and two pieces of capacitors 216 and 217, which constitute a current distributing circuit, a differential switching circuit, and an emitter follower. The circuit constant of the delay interpolator 12 is designed in such a way that a propagation delay between input and output thereof will be a desired delay rate d2.
In the fifth transistor 201 of the current distributing circuit, the base terminal is connected to a control terminal CTL1 of the delay interpolator 12, and the emitter terminal is connected to the fourth current source 209 through the resistor 212. In the sixth transistor 202 of the current distributing circuit, the base terminal is connected to an inverting control terminal /CTL1 of the delay interpolator 12, and the emitter terminal thereof is connected to the fourth current source 209 through the resistor 213.
In the seventh transistor 203 of the differential switching circuit, the base terminal is connected to the second input terminal SLW1 of the delay interpolator 12, the collector terminal is connected to the power supply terminal VCC through the loading resistor 214, and the emitter terminal is connected to the collector terminal of the fifth transistor 201. In the eighth transistor 204 of the differential switching circuit, the base terminal is connected to the second inverting input terminal /SLW1 of the delay interpolator 12, the collector terminal thereof is connected to the power supply terminal VCC through the loading resistor 215, and the emitter terminal is connected to the collector terminal of the fifth transistor 201.
In the ninth transistor 205 of the differential switching circuit, the base terminal is connected to the first input terminal FST1 of the delay interpolator 12, the collector terminal is connected to the collector terminal of the seventh transistor 203, and the emitter terminal is connected to the collector terminal of the sixth transistor 202. In the tenth transistor 206 of the differential switching circuit, the base terminal is connected to the first inverting input terminal /FST1 of the delay interpolator 12, the collector terminal is connected to the collector terminal of the eighth transistor 204, and the emitter terminal is connected to the collector terminal of the sixth transistor 202.
The capacitor 216 is connected in parallel with the resistor 214 between the collector terminal of the seventh and ninth transistors 203, 205 and the power supply terminal VCC. On the other hand, the capacitor 217 is connected in parallel with the resistor 215 between the collector terminal of the eight and tenth transistors 204, 206 and the power supply terminal VCC.
The collector terminal of the eighth transistor 204 is connected to the base terminal of the eleventh transistor 207 of the emitter follower. In the eleventh transistor 207, the collector terminal is connected to the power supply terminal VCC, and the emitter terminal is connected to the fifth current source 210 as well as to the output terminal OUT1 of the delay interpolator 12. The collector terminal of the seventh transistor 203 is connected to the base terminal of the twelfth transistor 208 of the emitter follower. In the twelfth transistor 208, the collector terminal is connected to the power supply terminal VCC, and the emitter terminal is connected to the sixth current source 211 as well as to the inverting output terminal /OUT1 of the delay interpolator 12.
The output terminal OUT1 of the delay interpolator 12 is connected to the inverting input terminal /IN of the delay unit 11 as well as to the first inverting input terminal /FST1 of the delay interpolator 12. The inverting output terminal /OUT1 of the delay interpolator 12 is connected to the input terminal IN of the delay unit 11 as well as to the first input terminal FST1 of the delay interpolator 12.
Herein, in the device shown in FIG. 14, although the phase of an output signal from the delay interpolator 12 is inverted at the inverting gate 13 and the inverted signal is inputted into the first input terminal FST1 of the delay interpolator 12 and the delay unit 11, the actual voltage controlling/oscillating device is designed in such a way that the differential output from the delay interpolator 12 is inputted with the phase thereof inverted into the first input terminal FST1 of the delay interpolator 12 as well as into the delay unit 11 in place of using the inverting gate 13 as shown in FIG. 15.
FIG. 16 is a timing chart for explaining an operational timing of the delay interpolator 12. Inputted into the second input terminal SLW1 of the delay interpolator 12 is the same signal as that inputted into the first input terminal FST1 with a delay equivalent to the propagation delay rate d1 in the delay unit 11. The delay interpolator 12 synthesizes the signals inputted into the first input terminal FST1 as well as into the second input terminal SLW1 respectively at a synthesizing ratio corresponding to the oscillation frequency control voltage VCTL inputted into the control terminal CTL1, and outputs the synthesized signal. A waveform V0(t) outputted from the delay interpolator 12 can be expressed with the help of the following Equation (2) and Equation (3) assuming that the synthesizing ratio is .beta.. EQU V0(t)=Vfst(t)+.beta.[Vslw(t)-Vfst(t)]=Vfst(t)+.beta..multidot.d1 (2)
where EQU 0.ltoreq..beta.1 (3)
From the Equation (2) and Equation (3), it is clear that the waveform of an output signal from the delay interpolator 12 is the same as that of the signal inputted into the first input terminal FST1 which is a waveform with the phase thereof is delayed by .beta..multidot.d1. The synthesizing ratio .beta. of the actual delay interpolator 12 is decided by changing a current distribution ratio of the fourth current source 209 utilizing the oscillation frequency control voltage VCTL fed to each base terminal of the pair of transistors 201 and 202.
Because the collector terminals of the pair of transistors 203 and 205 are commonly connected and also the collector terminals of the pair of transistors 204 and 206 are commonly connected, which are connected to the loading resistors 214 and 215 respectively, the waveform of an signal inputted into the first input terminal FST1 and the waveform of and signal inputted into the second input terminal SLW1 are synthesized. Herein, in the actual delay interpolator 12, as a propagation delay rate d2 specific to the delay interpolator 12 is added to a delay time indicated by .beta..multidot.d1, the waveform V0(t) of an output signal from the delay interpolator 12 can be expressed with the help of the following Equation (4). EQU V0(t)=Vfst(t)+.beta..multidot.d1+d2 (4)
Namely, an actual output signal from the delay interpolator 12 is the same as that inputted into the first input terminal FST1 and has a waveform with the phase thereof delayed by .beta..multidot.d1+d2. Herein, assuming that each input resistance and delay constant of the seventh to tenth transistors 203, 204, 205 and 206 are rb and Kdif respectively; each delay constant of the eleventh and twelfth transistors 207 and 208 is Keh; a cutoff angle frequency of the transistor is .omega.t; the resistance of the resistors 108 and 109 is RL; the current of the fourth current source 209 is IEE0, and the current of the fifth and sixth current sources 210 and 211 is IEE1, the propagation delay rate d2 can be expressed with the help of the following Equation (5). EQU d2=rb/ (RL.multidot..omega.t)+rb.multidot.Kdif.multidot.IEE0+In(2).multidot.RL.mu ltidot.Keh.multidot.IEE1 (5)
In Equation (5), the first term and second term in the right side thereof are each switching delay rate in the pairs of differential transistors 203, 204, 205, and 206 respectively, and the third term therein is a propagation delay rate in the emitter follower.
FIG. 17 is a timing chart for explaining an operational timing of the voltage controlling/oscillating device based on the conventional technology. The delay interpolator 12 synthesizes, as described above, an input signal into the first input terminal FST1 and an input signal into the second input terminal SLW1 at a synthesizing ratio according to the oscillation frequency control voltage VCTL inputted into the control terminal CTL1 and outputs the synthesized signal. The waveform of the output signal is the same as that of the input signal into the first input terminal FST1. The delay interpolator 12 forms a waveform with the phase thereof delayed by .beta..multidot.d1+d2. Namely, the change (indicated by timing T1 in FIG. 17) in a voltage level inputted into the first input terminal FST1 of the delay interpolator 12 is delayed by .beta..multidot.d1+d2, and outputted from the output terminal OUT1 of the delay interpolator 12 (timing T2).
As an output signal from the delay interpolator 12 is inputted with the phase thereof inverted by the inverting gate 13 into the first input terminal FST1 of the delay interpolator 12, the voltage level at the first input terminal FST1 is inverted at the point of time indicated by timing T2. Similarly, at the point of time indicated by timing T3 delayed by .beta..multidot.d1+d2 from timing T2, the voltage level at the first input terminal FST1 is inverted again and the voltage level of an output signal from the output terminal OUT1 is also inverted. By repeating this processing, the delay interpolator 12 outputs clock signals each of which output level is inverted at time intervals of .beta..multidot.d1+d2. Oscillation frequency fvco of this clock signal, minimum oscillation frequency fmin, maximum oscillation frequency fmax, and oscillation central frequency f0 thereof can be expressed with the help of the following Equation (6) to Equation (9) respectively. EQU fvco(.beta.)=1/[2.multidot.(.beta..multidot.d1+d2)] (6) EQU fmin=fvco(.beta.=0)=1/2[2.multidot.d2] (7) EQU fmax=fvco(.beta.=1)=1/2[2.multidot.(d1+d2)] (8) EQU f0=fvoc(.beta.=0.5)=1/(d1+2.multidot.d2) (9)
As described above, the conventional type of voltage controlling/oscillating device is designed, as clearly understood from the Equation (7) to Equation (9), to essentially control the oscillation frequency by setting a propagation delay rate d1 in the delay unit 11 and a propagation delay rate d2 in the delay interpolator 12 and adjusting an oscillation frequency control voltage VCTL for deciding .beta..
However, when the conventional type of voltage controlling/oscillating device is made into an integrated circuit, input resistance rb, delay constants Cdif, Keh, and a cutoff angle frequency .omega.t of a transistor and the resistance RL have generally more than .+-.10% of variations derived from variations in manufacturing in the applied process. Accordingly, even if propagation delay rates d1, d2 are designed to get the oscillation central frequency f0, there is a problem such that displacement may occur in an actual oscillation central frequency in a manufacturing step.
Generally, as the voltage controlling/oscillating device is used in many cases for a phase-locked loop (PLL), if the oscillation central frequency is displaced from a design value, a constant phase error in the phase-locked loop may occur, which is disadvantageous. Therefore, loading resistance RL of the delay unit 11 and delay interpolator 12 is adjusted by laser trimming, and displacement of the oscillation central frequency due to variations in process is corrected. In this method, however, as laser trimming is performed while an oscillation central frequency is measured when bare chips for an integrated circuit is selected, a costly measurement system such as a high frequency prober is required, which significantly increases the capital investment.